The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Sep. 10, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Te-Chang Hsu, Tainan, TW;

Chun-Chia Chen, Tainan, TW;

Yao-Jhan Wang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 29/7848 (2013.01);
Abstract

A fabricating method of a semiconductor structure includes providing a substrate divided into a dense region and an isolated region, wherein a first gate structure is disposed within the dense region, and a second gate structure is disposed within the isolated region. Then, a first material layer is formed to cover the first gate structure, the second gate structure and the substrate. Later, a second material layer is formed to cover the first material layer. After that, the second material layer within the dense region is entirely removed. Subsequently, a third material layer is formed to cover the isolated region and the dense region. Next, the substrate is etched to forma first recess at two sides of the first gate structure, and a second recess at two sides of the second gate structure. Finally, an epitaxial layer is formed to fill the first recess and the second recess.


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