The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Mar. 12, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Shantanu Kalchuri, San Jose, CA (US);

Brian Schieck, Hayward, CA (US);

Abraham Yee, Cupertino, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 23/34 (2006.01); H01L 23/433 (2006.01); H01L 25/16 (2006.01); H01L 23/367 (2006.01); H01L 23/42 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4334 (2013.01); H01L 25/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/42 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/92225 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1659 (2013.01); H01L 2924/16251 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01);
Abstract

Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.


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