The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2018
Filed:
Jun. 19, 2013
Applicant:
Netspeed Systems, San Jose, CA (US);
Inventors:
Joji Philip, San Jose, CA (US);
Joseph Rowlands, San Jose, CA (US);
Sailesh Kumar, San Jose, CA (US);
Assignee:
NETSPEED SYSTEMS, San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
H04J 3/0658 (2013.01); G06F 1/04 (2013.01);
Abstract
Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning.