The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Mar. 30, 2016
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Eric Lee, San Jose, CA (US);

Qiang Tang, Cupertino, CA (US);

Ali Feiz Zarrin Ghalam, Sunnyvale, CA (US);

Hoon Choi, Santa Clara, CA (US);

Daesik Song, Sunnyvale, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G06F 12/0802 (2016.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 12/0802 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/222 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G06F 2212/222 (2013.01); G06F 2212/7203 (2013.01);
Abstract

In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.


Find Patent Forward Citations

Lee, Eric. (2018). Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal (U.S. Patent No. 10019170). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10019170

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…