The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Nov. 22, 2013
Applicants:

Patrice Besse, Tournfeuille, FR;

Jean-philippe Laine, saint lys, FR;

Eric Pierre Rolland, Grepiac, FR;

Inventors:

Patrice Besse, Tournfeuille, FR;

Jean-Philippe Laine, saint lys, FR;

Eric Pierre Rolland, Grepiac, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/87 (2006.01); H01L 21/761 (2006.01); H01L 21/762 (2006.01); H01L 29/45 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 21/761 (2013.01); H01L 21/76264 (2013.01); H01L 27/0259 (2013.01); H01L 27/0292 (2013.01); H01L 29/87 (2013.01); H01L 29/0649 (2013.01); H01L 29/45 (2013.01);
Abstract

An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistorof the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.


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