The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Dec. 17, 2016
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Keiichi Maekawa, Tokyo, JP;

Shiro Kamohara, Tokyo, JP;

Yasushi Yamagata, Tokyo, JP;

Yoshiki Yamamoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 21/266 (2006.01); H01L 21/283 (2006.01); H01L 21/768 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 17/16 (2013.01); H01L 21/266 (2013.01); H01L 21/283 (2013.01); H01L 21/76895 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/36 (2013.01);
Abstract

To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.


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