The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Dec. 14, 2016
Applicant:

Elite Semiconductor Memory Technology Inc., Hsinchu, TW;

Inventors:

Tse-Hua Yao, Hsinchu County, TW;

Yi-Fan Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 8/10 (2006.01); G11C 8/06 (2006.01); G11C 29/12 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 29/78 (2013.01); G11C 8/06 (2013.01); G11C 8/10 (2013.01); G11C 17/16 (2013.01); G11C 29/12 (2013.01);
Abstract

A memory auto repairing circuit including: a decoding circuit, a latch enable circuit and a first latch circuit, wherein the decoding circuit is arranged to compare a first input address with a plurality of fail addresses to generate a control signal; the latch enable circuit is arranged to selectively generate a first enable signal at least according to the control signal; and the first latch circuit is arranged to receive the first input address, and store the first input address when the first enable signal is received by the first latch circuit; wherein when the control signal indicates that the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted from the latch enable circuit to the first latch circuit.


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