The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Mar. 27, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Michael LeMay, Hillsboro, OR (US);

Ravi L. Sahita, Beaverton, OR (US);

Beeman C. Strong, Portland, OR (US);

Thilo Schmitt, Biberach/Riβ, DE;

Yuriy Bulygin, Beaverton, OR (US);

Markus T. Metzger, Ulm, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/56 (2013.01); G06F 21/44 (2013.01); G06F 21/52 (2013.01);
U.S. Cl.
CPC ...
G06F 21/56 (2013.01); G06F 21/44 (2013.01); G06F 21/52 (2013.01);
Abstract

Technologies for control flow exploit mitigation include a computing device having a processor with real-time instruction tracing support. During execution of a process, the processor generates trace data indicative of control flow of the process. The computing device analyzes the trace data to identify suspected control flow exploits. The computing device may use heuristic algorithms to identify return-oriented programming exploits. The computing device may maintain a shadow stack based on the trace data. The computing device may identify indirect branches to unauthorized addresses based on the trace data to identify jump-oriented programming exploits. The computing device may check the trace data whenever the process is preempted. The processor may detect mispredicted return instructions in real time and invoke a software handler in the process space of the process to verify and maintain the shadow stack. Other embodiments are described and claimed.


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