The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Jan. 25, 2016
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Botang Shao, Austin, TX (US);

Timothy J. Strauss, Granger, IN (US);

Thomas Jew, Austin, TX (US);

Edward Bryann C. Fernandez, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/27 (2006.01); G06F 11/263 (2006.01); G06F 11/273 (2006.01); G11C 29/14 (2006.01); G11C 29/18 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G06F 11/27 (2013.01); G06F 11/263 (2013.01); G06F 11/273 (2013.01); G11C 29/14 (2013.01); G11C 29/18 (2013.01); G11C 2029/1206 (2013.01);
Abstract

A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).


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