The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Aug. 21, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ming-Huei Weng, Hsin-Chu, TW;

Ching-Yu Chang, Hsin-Chu, TW;

Chun-Kuang Chen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/11 (2006.01); G03F 7/00 (2006.01); G03F 7/20 (2006.01); G03F 7/32 (2006.01); G03F 7/38 (2006.01);
U.S. Cl.
CPC ...
G03F 7/0035 (2013.01); G03F 7/2022 (2013.01); G03F 7/32 (2013.01); G03F 7/38 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming a first photoresist layer over a substrate, over which a protective layer material is deposited to form a protective layer. A second photoresist layer is formed over the protective layer. A first lithography exposure process is performed, through a first mask, to expose the first and second photoresist layers, and to form a bottom latent pattern. A second lithography exposure process is performed, through a second mask, to expose the first and second photoresist layers, and to form a top latent pattern, where the top latent pattern at least partially overlaps the bottom latent pattern. The first and second photoresist layers and the protective layer are developed to form a first main feature and a second main feature from the bottom and top latent patterns respectively, and an opening in the protective layer vertically aligned with the second main feature.


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