Company Filing History:
Years Active: 2013-2014
Title: Innovations of Yu-Lun Wang
Introduction
Yu-Lun Wang is a notable inventor based in Tainan, Taiwan. He has made significant contributions to the field of low-density parity-check codecs, showcasing his expertise through his innovative patents. With a total of 2 patents, Wang continues to push the boundaries of technology.
Latest Patents
Wang's latest patents focus on low-complexity and multi-mode Low-density Parity-check (LDPC) codecs. The first patent provides a codec where decoding operations are divided into small tasks, allowing for a unified hardware implementation. This design enables the reuse of hardware resources across different modes. Additionally, memory access is facilitated through routing networks with fixed interconnections and memory address generators, which reduces the complexity of hardware implementation. The invention also includes an early termination function that allows iterative operations to be halted when a specific threshold is reached, thereby reducing power consumption. The hardware resources for early termination share components with an encoder, further minimizing complexity.
The second patent mirrors the first, emphasizing the same innovative features and benefits of the low-complexity LDPC codec. This consistency in design highlights Wang's commitment to enhancing efficiency and performance in codec technology.
Career Highlights
Yu-Lun Wang is affiliated with Tsinghua University, where he contributes to research and development in his field. His work at the university allows him to collaborate with other experts and advance the study of coding techniques.
Collaborations
Wang has worked alongside Yeong-Luh Ueng, a fellow researcher, to further explore advancements in codec technology. Their collaboration has likely contributed to the innovative nature of Wang's patents.
Conclusion
Yu-Lun Wang's contributions to low-density parity-check codecs demonstrate his innovative spirit and dedication to technology. His patents reflect a commitment to improving efficiency and reducing complexity in hardware implementations.