Seoul, South Korea

Yonglk Choi

This inventor holds 1 USPTO granted patent. Top assignee: Avago Technologies International Sales Pte. Limited. Active years: 2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yonglk Choi. Retrieved from https://idiyas.com/inventor/yonglk-choi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2025

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1 patent (USPTO):Explore Patents

Title: Yonglk Choi: Innovator in Solder Bump Technology

Introduction

Yonglk Choi is a notable inventor based in Seoul, South Korea. He has made significant contributions to the field of electronics through his innovative designs and patents. His work focuses on improving mechanical, electrical, and thermal performance in electronic modules.

Latest Patents

Yonglk Choi holds a patent for a "Device having solder bump structure for improved mechanical, electrical, and/or thermal performance." This patent describes a module designed to enhance performance through a unique solder bump configuration. The module features a bottom surface and side surface, with two solder bumps strategically placed to optimize functionality. The design allows for improved mechanical and thermal performance, making it a valuable contribution to the electronics industry.

Career Highlights

Yonglk Choi is currently employed at Avago Technologies International Sales Pte. Limited, where he continues to innovate and develop new technologies. His expertise in solder bump structures has positioned him as a key player in the field of electronic components.

Collaborations

Yonglk Choi collaborates with his coworker, Ah Ron Lee, to further enhance their projects and drive innovation within their company.

Conclusion

Yonglk Choi's contributions to solder bump technology exemplify his commitment to advancing the electronics industry. His innovative designs and patents reflect his expertise and dedication to improving performance in electronic modules.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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