For the Inventor, By the Inventor

Enter inventor name

Jersey City, NJ, United States of America

Stefanos Kaxiras

USPTO Granted Patents = 8

EPO Patents = 2

Average Co-Inventor Count = 3.1

ph-index = 7

Forward Citations = 157(Granted Patents)

Location History:

Jersey City, NJ (US) (2003 - 2006)
Patras, GR (2008)
Ioannina, GR (2009)

Company Filing History:

Agere Systems Inc.

Princeton University

where one patent can have more than one assignee

Years Active: 2003-2009

Loading Chart...

Loading Chart...

8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7573880 - Set-associative memory architecture for routing tables (2009-08-11),

2. 7472302 - Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay (2008-12-30),

3. 7096343 - Method and apparatus for splitting packets in multithreaded VLIW processor (2006-08-22),

4. 7007153 - Method and apparatus for allocating functional units in a multithreaded VLIW processor (2006-02-28),

5. 6983388 - Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines (2006-01-03),

6. 6889293 - Directory-based prediction methods and apparatus for shared-memory multiprocessor systems (2005-05-03),

7. 6665791 - Method and apparatus for releasing functional units in a multithreaded VLIW processor (2003-12-16),

8. 6658551 - Method and apparatus for identifying splittable packets in a multithreaded VLIW processor (2003-12-02),

This text is generated by artificial intelligence and may not be accurate.

Please report any incorrect information to support@idiyas.com

Loading…