Ssu-Yen Wu

Title: Ssu-Yen Wu: Innovator in Clock Gating Technology

Introduction

Ssu-Yen Wu is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of electronics, particularly in the area of clock gating technology. His innovative work has led to the development of a patented technology that enhances the efficiency of electronic circuits.

Latest Patents

Ssu-Yen Wu holds a patent for a clock gating cell. This invention includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal, generating a first enable signal based on the first clock signal. The output stage, coupled to the input stage, receives the first enable signal and the first clock signal, producing a clock gating signal accordingly. Notably, the input stage operates based on a first voltage threshold, while the output stage operates on a different second voltage threshold, enhancing the functionality of electronic devices. He has 1 patent to his name.

Career Highlights

Ssu-Yen Wu is currently employed at MediaTek Corporation, a leading global semiconductor company. His role at MediaTek allows him to apply his expertise in developing advanced technologies that drive innovation in the electronics industry.

Collaborations

Throughout his career, Ssu-Yen Wu has collaborated with notable colleagues, including Kin-Hooi Dia and Shih-Yun Lin. These collaborations have contributed to the advancement of technology in their respective fields.

Conclusion

Ssu-Yen Wu's contributions to clock gating technology exemplify his innovative spirit and dedication to advancing electronic circuit design. His work continues to influence the industry and inspire future innovations.