San Jose, CA, United States of America

Perumal R Subramonium

This inventor holds 4 USPTO granted patents. Top assignee: Apple Inc.. Active years: 2015-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Perumal R Subramonium. Retrieved from https://idiyas.com/inventor/perumal-r-subramonium

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.8

ph-index = 2

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2015-2017

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4 patents (USPTO):Explore Patents

Title: Innovations of Perumal R Subramonium

Introduction

Perumal R Subramonium is a notable inventor based in San Jose, CA. He has made significant contributions to the field of cache memory technology, holding a total of 4 patents. His work focuses on improving the efficiency and performance of cache memory systems.

Latest Patents

One of his latest patents is titled "Selective cache way-group power down." This invention describes a method and apparatus for selectively powering down a portion of cache memory based on access conditions. The process involves determining a power down condition and selecting a group of cache ways to lock and flush before activating a low power mode. Another significant patent is "Least recently used mechanism for cache line eviction from a cache memory." This mechanism outlines a method for evicting cache lines by selecting the least recently used lines, ensuring optimal memory management.

Career Highlights

Perumal R Subramonium is currently employed at Apple Inc., where he continues to innovate in the field of technology. His work has been instrumental in enhancing the performance of cache memory systems, which are critical for modern computing.

Collaborations

He has collaborated with notable colleagues such as Mahnaz P Sadoughi-Yarandi and Brian P Lilly, contributing to various projects that advance technology in the industry.

Conclusion

Perumal R Subramonium's contributions to cache memory technology through his patents reflect his expertise and commitment to innovation. His work continues to influence the field and improve computing efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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