Santa Clara, CA, United States of America

Pat Zicolello


Average Co-Inventor Count = 2.0

ph-index = 2

Forward Citations = 14(Granted Patents)


Company Filing History:


Years Active: 1997-1998

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2 patents (USPTO):Explore Patents

Title: Pat Zicolello: Innovator in Semiconductor Technology

Introduction

Pat Zicolello is a notable inventor based in Santa Clara, CA (US). He has made significant contributions to the field of semiconductor technology, particularly in methods to prevent cracks in semiconductor dies. With a total of 2 patents to his name, Zicolello's work has had a meaningful impact on the industry.

Latest Patents

Zicolello's latest patents focus on a method and apparatus for preventing cracks in semiconductor dies. The innovation involves an anchor structure placed in open fields in corner areas of the semiconductor die and along die edges. This design aims to prevent cracks by positioning the anchor structure perpendicular to the resultant vector force, which is approximately at a 45-degree angle to an imaginary horizontal line passing through the die. This strategic placement helps to more uniformly distribute stresses along the anchor, thereby preventing corner cracks in the die. Additionally, along the die edges, the anchor structures are placed approximately perpendicular to the resultant vector forces that impact the die edges.

Career Highlights

Zicolello is currently employed at Cypress Semiconductor Corporation, where he continues to develop innovative solutions in semiconductor technology. His work has been instrumental in enhancing the reliability and performance of semiconductor devices.

Collaborations

Zicolello collaborates with various professionals in his field, including his coworker Marc D Hartranft. Their combined expertise contributes to the advancement of semiconductor technologies.

Conclusion

Pat Zicolello's contributions to semiconductor technology through his innovative patents demonstrate his commitment to improving the industry. His work not only addresses critical challenges but also paves the way for future advancements in semiconductor design and reliability.

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