Minoru Kayano

Title: Minoru Kayano: Innovator in Bit Synchronization and IC Design

Introduction

Minoru Kayano is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the fields of bit synchronization circuits and integrated circuit (IC) design. With a total of 2 patents, his work showcases innovative solutions that enhance the performance and efficiency of electronic systems.

Latest Patents

One of Kayano's latest patents is a bit synchronization circuit. This circuit extracts the central phase of an eye opening irrespective of a jitter distribution of input data to maintain an optimum timing adjustment margin. The bit synchronization circuit features a data edge detector that compares the phases of an edge of the input data and m-phase clock signals divided from a reference clock. Data edge phase information from the data edge detector is accumulated by a phase accumulation register, which stores the jitter distribution of the input data as accumulated phase information. Based on this accumulated phase information, an eye center phase calculator decodes the negative and positive ends of a jitter range as negative jitter range information and positive jitter range information. It then calculates a phase control direction in relation to an extracted phase value that represents a presently selected clock phase. A correction circuit extracts the positional relationship between the present eye opening width and the extracted phase value, clearing the accumulated phase information to increase the eye opening width.

Another notable patent involves an IC comprising functional blocks for which a mask pattern is patterned. Each functional block consists of a plurality of macroblocks, and each macroblock comprises a plurality of basic cells. The mask pattern is patterned according to a layout design using the connection data of the macroblocks and the placement data of the basic cells. This systematic arrangement allows for the shortest possible connections and the narrowest possible area for each functional block. To operate the patterning of the mask pattern, an operating system is utilized, which includes first and second memories loaded with the connection and placement data, respectively.

Career Highlights

Minoru Kayano is currently employed at NEC Corporation, where he continues to innovate and develop cutting-edge technologies. His work has significantly impacted the field of electronics, particularly in enhancing the performance of integrated circuits.

Collaborations

Throughout his career, Kayano has collaborated with notable colleagues, including Yasushi Aoki and Mitsuo Baba. These collaborations have contributed to the advancement of technology in their respective fields.

Conclusion