Company Filing History:
Years Active: 2023-2025
Title: Innovations of Krishnaiah Gummidipudi
Introduction
Krishnaiah Gummidipudi is a notable inventor based in Bengaluru, India. He has made significant contributions to the field of technology, particularly in processor design and memory management. With a total of 3 patents, Gummidipudi's work reflects his expertise and innovative spirit.
Latest Patents
One of his latest patents is titled "Last level cache hierarchy in chiplet based processors." This invention describes an accelerated processor that includes a processor core die with multiple compute units, featuring a first level (L1) cache. Additionally, it incorporates several memory cache dies connected to the processor core die, which includes a last level cache (LLC) such as a level 3 (L3) cache. The patent outlines an LLC controller that issues cache access requests and directs them based on latency to a subset of the memory cache dies.
Another significant patent is "Configurable apron support for expanded-binning." This disclosure presents systems and methods for configurable aprons for expanded binning. It involves identifying pixel tiles in bins and determining edge information for each tile. The invention further explores whether adjacent bins are visible based on the edge information of the pixel tiles.
Career Highlights
Gummidipudi has worked with prominent companies in the technology sector, including Qualcomm Incorporated and Advanced Micro Devices Corporation. His experience in these organizations has contributed to his development as an inventor and innovator.
Collaborations
Some of his notable coworkers include Andrew Evan Gruber and Pavan Kumar Akkaraju. Their collaboration has likely fostered an environment of innovation and creativity in their respective projects.
Conclusion
Krishnaiah Gummidipudi's contributions to technology through his patents and work with leading companies highlight his role as a significant inventor in the field. His innovative solutions continue to influence advancements in processor design and memory management.