Location History:
- Plainsboro, NJ (US) (1999 - 2001)
- Princeton, NJ (US) (2002)
Company Filing History:
Years Active: 1999-2002
Title: Innovations of Kiran B Doreswamy
Introduction
Kiran B Doreswamy is a notable inventor based in Princeton, NJ, who has made significant contributions to the field of circuit testing. With a total of four patents to his name, he has developed innovative methods that enhance the efficiency and effectiveness of testing sequential circuits.
Latest Patents
One of his latest patents is titled "Segmented compaction with pruning and critical fault elimination." This method involves generating a vector set used for testing sequential circuits by selecting multiple fault models and identifying associated fault lists and vector sets. The process includes compacting these vector sets to ensure that all faults are identified or that any drop in fault list coverage remains within a specified tolerance limit. Another significant patent is "On-line partitioning for sequential circuit test generation." This method addresses test generation problems by recursively dividing them into smaller, manageable sub-problems. It emphasizes the reuse of solutions for dependent sub-problems and identifies minimal subsets of conflicting objectives when necessary.
Career Highlights
Kiran B Doreswamy is currently employed at NEC USA, Inc., where he continues to innovate in the field of circuit testing. His work has been instrumental in advancing methodologies that improve the reliability of electronic circuits.
Collaborations
He collaborates with talented coworkers such as Srimat T Chakradhar and Surendra K Bommu, contributing to a dynamic and innovative work environment.
Conclusion
Kiran B Doreswamy's contributions to circuit testing through his patents reflect his expertise and commitment to innovation. His work continues to influence the field and enhance the reliability of electronic systems.