Karthik Narayanan Subramanian

Title: Karthik Narayanan Subramanian: Innovator in Low Power Design Testing

Introduction

Karthik Narayanan Subramanian is a notable inventor based in San Jose, CA. He has made significant contributions to the field of low power design testing, holding a total of 4 patents. His work focuses on improving the efficiency and reliability of electronic circuits.

Latest Patents

One of his latest patents is titled "Unified approach for improved testing of low power designs with clock gating cells." This invention includes an apparatus that comprises a core logic circuit, integrated clock-gating (ICG) cells, and ICG control cells (ICCs). The core logic circuit consists of multiple flip-flops connected to form scan chains, with ICG cells configured to gate clock signals of these chains. Another significant patent is "Synchronized clocks to detect inter-clock domain transition defects." This apparatus features a first circuit generating a launch signal synchronized with a first clock signal and a second circuit that receives a second clock signal to generate pulses in third and fourth clock signals.

Career Highlights

Karthik has worked with prominent companies such as Cisco Technology, Inc. and Ambarella International LP. His experience in these organizations has allowed him to develop innovative solutions in the field of electronic design automation.

Collaborations

Some of his notable coworkers include Dheerendra Talur and Praveen Kumar Jaini. Their collaboration has contributed to the advancement of technology in low power design.

Conclusion

Karthik Narayanan Subramanian is a distinguished inventor whose work in low power design testing has led to several impactful patents. His contributions continue to influence the field of electronic circuit design.