Jih-Sheng Shen

Title: Jih-Sheng Shen: Innovator in NoC Timing Power Estimation

Introduction

Jih-Sheng Shen is a prominent inventor based in Tainan, Taiwan. He has made significant contributions to the field of network-on-chip (NoC) technology, particularly in power estimation methods. His innovative approach has the potential to enhance the efficiency of electronic systems.

Latest Patents

One of Jih-Sheng Shen's notable patents is a "NoC timing power estimating device and method thereof." This patent outlines a method that includes estimating the transmission timing of multiple transmission units. The method indicates the time points at which these units enter and leave various passing elements of the NoC. By analyzing the transmission timing, the method estimates the circuit and power states of the passing elements, ultimately allowing for the estimation of power consumption within the NoC.

Career Highlights

Jih-Sheng Shen is affiliated with the Industrial Technology Research Institute, where he continues to work on advancing technology in his field. His expertise in NoC technology has positioned him as a key figure in research and development.

Collaborations

Throughout his career, Jih-Sheng Shen has collaborated with notable colleagues, including Ting-Shuo Hsu and Jing-Jia Liou. These collaborations have contributed to the advancement of research in NoC technology and power estimation methods.

Conclusion

Jih-Sheng Shen's work in NoC timing power estimation showcases his innovative spirit and dedication to improving electronic systems. His contributions are vital to the ongoing development of efficient technologies in the field.