Jayanta Bahadra

Title: Jayanta Bahadra: Innovator in Integrated Circuit Design Verification

Introduction

Jayanta Bahadra is a notable inventor based in Austin, TX, who has made significant contributions to the field of integrated circuit design. His innovative approach to design verification has led to the development of a unique technique that enhances the reliability of integrated circuits.

Latest Patents

Jayanta holds a patent for "Integrated circuit design verification through forced clock glitches." This technique involves identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and determining clock signals for each of these elements. The process includes generating assertions for the identified clock signals and pinpointing potential glitchy logic in the respective clock paths. By inserting glitches into these paths, Jayanta's method provides a modified RTL file that can be used for executing RTL simulations, thereby ensuring the robustness of the design.

Career Highlights

Jayanta Bahadra is currently employed at Freescale Semiconductor, Inc., where he applies his expertise in integrated circuit design. His work has been instrumental in advancing the reliability and performance of semiconductor technologies.

Collaborations

Throughout his career, Jayanta has collaborated with talented individuals such as Xiushan Feng and Xiao Sun, contributing to various projects that push the boundaries of integrated circuit technology.

Conclusion

Jayanta Bahadra's innovative techniques in integrated circuit design verification exemplify the importance of creativity and collaboration in the field of technology. His contributions continue to influence the development of reliable semiconductor solutions.