München, Germany

Jürgen Weidenhöfer


Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 9(Granted Patents)


Company Filing History:


Years Active: 2004

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1 patent (USPTO):Explore Patents

Title: Jürgen Weidenhöfer: Innovator in Integrated Circuit Testing

Introduction

Jürgen Weidenhöfer is a notable inventor based in München, Germany. He has made significant contributions to the field of integrated circuit testing, particularly in the development of innovative testing configurations and methods.

Latest Patents

Weidenhöfer holds a patent for a "Test configuration and test method for testing a plurality of integrated circuits in parallel." This invention focuses on a test configuration designed to test multiple integrated circuits, especially fast semiconductor memory modules located on a wafer, simultaneously. The configuration includes a carrier board that connects electrical signal lines to a test system, contact-making needles for establishing electrical connections with the circuits, and several active modules arranged on the carrier board. Each active module is dedicated to one of the circuits being tested in parallel, effectively inserted into the signal path between the test system and the respective circuit.

Career Highlights

Jürgen Weidenhöfer is associated with Infineon Technologies AG, a leading company in semiconductor solutions. His work at Infineon has allowed him to contribute to advancements in technology that enhance the efficiency and effectiveness of integrated circuit testing.

Collaborations

Throughout his career, Weidenhöfer has collaborated with notable colleagues, including Michael Hübner and Gunnar H. Krause. These collaborations have fostered an environment of innovation and have led to the development of cutting-edge technologies in the semiconductor industry.

Conclusion

Jürgen Weidenhöfer's contributions to integrated circuit testing exemplify the importance of innovation in technology. His patent and work at Infineon Technologies AG highlight his role as a key figure in advancing semiconductor testing methodologies.

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