Jacobus Verbree

Title: Jacobus Verbree: Innovator in 3D Stacked Integrated Circuits

Introduction

Jacobus Verbree is a notable inventor based in Hierden, Netherlands. He has made significant contributions to the field of integrated circuits, particularly in the area of 3D stacked integrated circuits (3D-SICs). His innovative work has led to the development of a unique test access architecture that enhances the testing process for these advanced technologies.

Latest Patents

Jacobus Verbree holds a patent for a "Test access architecture for TSV-based 3D stacked ICS." This patent describes a test access architecture that facilitates both pre-bond die testing and post-bond stack testing. The architecture employs a modular test approach, allowing various dies, their embedded IP cores, inter-die TSV-based interconnects, and external I/Os to be tested as separate units. This modularity optimizes the 3D-SIC test flow and builds upon existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack through a test structure known as a wrapper unit.

Career Highlights

Throughout his career, Jacobus Verbree has worked with prominent organizations, including Imec and Stichting Imec Nederland. His experience in these companies has allowed him to refine his expertise in integrated circuit design and testing methodologies. His contributions have been instrumental in advancing the capabilities of 3D-SIC technology.

Collaborations

Jacobus has collaborated with notable professionals in his field, including Erik Jan Marinissen and Mario Konijnenburg. These collaborations have further enriched his work and contributed to the development of innovative solutions in integrated circuit testing.

Conclusion

Jacobus Verbree is a distinguished inventor whose work in 3D stacked integrated circuits has paved the way for advancements in testing methodologies. His patent and career achievements reflect his commitment to innovation in the field of integrated circuits.