Cupertino, CA, United States of America

Jacob Greidinger


Average Co-Inventor Count = 6.0

ph-index = 3

Forward Citations = 119(Granted Patents)


Company Filing History:


Years Active: 1997-1999

Loading Chart...
3 patents (USPTO):Explore Patents

Title: Jacob Greidinger: Innovator in Integrated Circuit Design

Introduction

Jacob Greidinger is a notable inventor based in Cupertino, CA (US). He has made significant contributions to the field of integrated circuit design, holding a total of 3 patents. His work focuses on improving the efficiency and effectiveness of digital circuit design through innovative methods and apparatus.

Latest Patents

One of Jacob's latest patents is titled "Method and apparatus for making integrated circuits by inserting buffers." This invention discloses a method and apparatus for creating digital integrated circuits while considering ramp delay and clock skew as constraints. The goal is to minimize the number of inserted buffers and the overall wire length connecting components for large clock trees. The invention involves developing a set of circuit specifications, including maximum clock skew, minimum driveability, and maximum ramp delay, which are described in a hardware description language on a digital computer system. A netlist is synthesized from this hardware description, and a modified netlist is formed by analyzing the netlist and inserting buffers to meet the circuit specifications. Ultimately, a digital integrated circuit is produced as specified by the modified netlist.

Another significant patent is the "Method for automatically routing circuits of very large scale." This invention introduces an automated routing tool designed for routing interconnections between circuit elements, standard cells, and cell blocks of cell-based designs. It combines the best features of both gate array routing techniques and cell-based routing techniques. The method eliminates the disadvantages of allowing the detailed router to adjust the relative positions of circuit elements during the detailed routing process. A topology manager is employed to iteratively compact the circuit topology while optimizing the routing of interconnections. The method utilizes bin-based global routing, which identifies expandable boundaries and provides input to a compaction routine that adjusts the expandable areas based on the global routing results.

Career Highlights

Jacob Greidinger has worked with prominent companies in the technology sector, including VLSI Technology, Inc. and VSLI Technology, Inc. His experience in these organizations has contributed to his expertise in integrated circuit design and innovation.

Collaborations

Throughout his career, Jacob has collaborated with talented individuals such as Mark R Hartoog and Ying-Meng Li. These collaborations have likely enriched his work and contributed to the development of his innovative patents.

Conclusion

Jacob Greidinger is a distinguished inventor whose work in integrated circuit

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…