Centreville, VA, United States of America

Ho Gia Phan


Average Co-Inventor Count = 3.0

ph-index = 4

Forward Citations = 55(Granted Patents)


Location History:

  • Centreville, VA (US) (2001)
  • Saratoga, CA (US) (2001)

Company Filing History:


Years Active: 2001

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4 patents (USPTO):Explore Patents

Title: The Innovations of Ho Gia Phan

Introduction

Ho Gia Phan is an accomplished inventor based in Centreville, VA (US). He has made significant contributions to the field of memory technology, holding a total of 4 patents. His work focuses on enhancing the reliability of static random access memory (SRAM) cells against single event upsets.

Latest Patents

Among his latest patents is a method and apparatus for hardening a static random access memory cell from single event upsets. This invention includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The design ensures that two inversion paths are formed between the cross-coupled transistors and the isolation transistors, thereby improving memory cell resilience. Another notable patent is a multiplexor featuring a single event upset (SEU) immune data keeper circuit. This multiplexor comprises a precharge transistor, an isolation transistor, an inverter, and an SEU immune storage cell, which enhances data integrity during potential disruptions.

Career Highlights

Ho Gia Phan has worked with notable companies, including BAE Systems, Inc. His experience in the industry has allowed him to develop innovative solutions that address critical challenges in memory technology.

Collaborations

Throughout his career, Ho Gia Phan has collaborated with talented individuals such as Bin Li and Derwin Jallice. These partnerships have contributed to the advancement of his inventions and the overall progress in the field.

Conclusion

Ho Gia Phan's contributions to memory technology through his patents demonstrate his commitment to innovation and excellence. His work continues to influence the development of more reliable memory systems.

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