Douglas J Feist

Title: Douglas J Feist: Innovator in Integrated Circuit Testing

Introduction

Douglas J Feist is a notable inventor based in Fort Collins, CO (US). He has made significant contributions to the field of integrated circuit (IC) testing, holding a total of 4 patents. His work focuses on improving the reliability and efficiency of clock jitter testing and analysis within integrated circuits.

Latest Patents

Feist's latest patents include innovative methods and structures for on-chip clock jitter testing and analysis. This invention provides a means for acquiring samples of an application clock signal within an IC and counting the number of samples that meet predetermined criteria. The count is then compared to acceptable limits to generate a pass/fail signal for the IC's use by external automation. Additionally, he has developed a sample clock based on the reference clock used by a Phase Locked Loop (PLL) circuit, which incorporates an incremental delay to effectively sense clock jitter at various points of the waveform. Another significant patent is the scan test expansion module, which serves as an interface between an automated tester and a device under test. This module includes a scan pattern memory and a failure log memory, facilitating efficient testing and data collection.

Career Highlights

Throughout his career, Douglas J Feist has worked with prominent companies such as LSI Logic Corporation and LSI Corporation. His experience in these organizations has allowed him to refine his skills and contribute to advancements in IC technology.

Collaborations

Feist has collaborated with notable colleagues, including Kevin J Gearhardt and Scott C Savage, further enhancing his work in the field of integrated circuits.

Conclusion

Douglas J Feist's contributions to integrated circuit testing through his innovative patents have significantly impacted the industry. His work continues to influence the development of reliable and efficient testing methods for integrated circuits.