Company Filing History:
Years Active: 2014
Title: Adam D Eldredge: Innovator in Clock Generation Technology
Introduction
Adam D Eldredge is a notable inventor based in Austin, TX (US). He has made significant contributions to the field of clock generation technology, particularly through his innovative patent. His work focuses on reducing frequency drift in low-jitter clock signals, which is crucial for various electronic applications.
Latest Patents
Adam D Eldredge holds a patent for a "Cascaded PLL for reducing low-frequency drift in holdover mode." This invention presents a cascaded phase-locked loop (PLL) clock generation technique that effectively minimizes frequency drift in a low-jitter clock signal during holdover mode. The apparatus includes a first PLL circuit that generates a control signal based on a first clock signal and a first divider value. Additionally, it features a second PLL circuit that produces the first clock signal from a low-jitter clock signal and a second divider value. A third PLL circuit is also included, which generates the second divider value based on the first clock signal, a third divider value, and a second clock signal. This innovative approach addresses the temperature dependence of the low-jitter clock signal compared to the second clock signal, which may exhibit higher jitter.
Career Highlights
Adam D Eldredge is currently employed at Silicon Laboratories Inc., where he continues to develop cutting-edge technologies. His expertise in PLL circuits and clock generation has positioned him as a valuable asset in the field of electronics.
Collaborations
Throughout his career, Adam has collaborated with esteemed colleagues such as Susumu Hara and Jeffrey S Batchelor. These partnerships have contributed to the advancement of technology in their respective areas of expertise.
Conclusion
Adam D Eldredge is a prominent inventor whose work in clock generation technology has made a significant impact. His innovative patent demonstrates his commitment to advancing electronic systems and reducing frequency drift in clock signals.