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For the Inventor, By the Inventor

JP

Sii R&d Center Inc.


USPTO Granted Patents = 2

Forward Citations = 2

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2 inventors (with patents filed for the assignee):

goldMedal Keiji Sato (2 out of 80 patents)

silverMedal Yutaka Saito (2 out of 57 patents)


2 patents:

1. 5960256 - Wafer layout of semiconductor device and manufacturing method thereof (1999-09-28),
2. 5872386 - Wafer layout of semiconductor device (1999-02-16),
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USPTO Data Jan 1 1976 - Dec 9 2025

2 Patents

#604 in

#10,988 in Japan

...
JP

Sii R&d Center Inc.

Forward Citations = 2

2 inventors:

goldMedal Keiji Sato (2 out of 80 patents)

silverMedal Yutaka Saito (2 out of 57 patents)

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