Sr. Principle Engineer at NVIDIA.
Patent №: 12132137 (October 29, 2024) – Continuous compositional grading for realization of low charge carrier barriers in electro-optical heterostructure semiconductor devices.
Processes for continuous compositional grading in electro-optical devices involve forming a first semiconductor layer, adding a graded layer, and then a second layer with a different bandgap.
Patent №: 12130473 (October 29, 2024) – Optical coupler. An optical interconnect device includes an in-plane laser cavity, a Franz Keldysh (FK) optical modulator, and a mode-transfer module with a tapered structure to expand the light beam for alignment with an external optical fiber. A universal coupler directs the light to an in-plane or perpendicular fiber, depending on orientation, and is coated with a reflective material.
Software Engineer at Meta.
Patent №: 12130725 (October 29, 2024) – Memory page markings as logging cues for processor-based execution tracing.
Cache-based tracing involves categorizing memory regions as logged or not logged. A computer system identifies a memory region in a logging state, updates a data structure to mark it as logged, and marks another region as not logged. This structure is shared with the processor, which then initiates or skips logging based on the memory address categorization, context, or access type.
Director of Technology at Applied Materials.
Patent №: 12131952 (October 29, 2024) – Wafer dicing using femtosecond-based laser and plasma etch.
Described are methods for dicing semiconductor wafers with multiple integrated circuits. A mask is applied to protect the circuits, and a laser scribing process patterns the mask and creates partial trenches between the circuits. The wafer is then plasma etched through these trenches to extend them, singulating the circuits. Each trench extension retains the original trench width.
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