Centurion+ Patent Holders as of September 24, 2024

His previous work in SSD includes areas such as caching, data policies, write amplification mitigation, endurance and reliability improvement, and media management policies. Additionally, he has extensive experience with FTL (Flash Translation Layer) modeling and workload analysis.

In terms of NAND technology, Muchherla has worked on NAND algorithms, electrical failure analysis, testing, qualification, and data mining & analysis. He has shared his expertise through notable conference appearances, including a panel talk at IMW 2022 and an invited talk at IRPS 2023

Patent №: 12099725 (September 24, 2024) – Code rate as function of logical saturation. The method involves determining the logical saturation of a memory device and adjusting its code rate accordingly. The code rate represents the ratio of user data to the total data, which includes both user and error correction data.

His current research and managerial focus is on wireless communication for automotive applications and related use cases, which are critical for the growing intersection of telecommunications and the automotive industry, particularly in connected and autonomous vehicles.

Patent №: 12101817 (September 24, 2024) – PRACH detection in a radio access network. A method for operating a network node in a radio access network involves detecting PRACH transmissions from user equipment across multiple time intervals, with different weights assigned to each interval. Related devices and methods are also disclosed.

Patent №: 12101728 (September 24, 2024) –  Configuration of additional synchronization signal. In some embodiments, a network node method includes determining if an additional synchronization signal should be transmitted to wireless devices and transmitting an indication of its availability. If needed, the indication informs the devices of the signal’s presence.

His leadership in memory system design continued at Sony Corporation in 2004, where he was the General Manager of the Memory System Department in the System LSI Business Division. In 2007, Sakui joined Intel Corporation’s NAND Products Group as a Research Scientist, followed by a move to Micron Technology in 2010, where he became a Senior Architect and Technologist in memory innovations, specializing in 3D NAND development.

Sakui has held numerous academic positions, including Visiting Professor roles at Tohoku University (2009), Tokyo Institute of Technology (2018), and Waseda University since 2009. He has also been a Principal Scientist at the Honda Research Institute Japan since 2017.

Dr. Sakui is also an IEEE Fellow, recognized for his contributions to NAND flash memory technology, and has received prestigious awards such as the Kanagawa Governor Patent Award (1997) and the Kanto District Patent Award (2005).

Patent №: 12101925 (September 24, 2024) – Memory device using semiconductor elements. A substrate has an N layer connected to a source line (SL) and another N layer connected to a bit line (BL) at opposite ends of a vertically standing Si pillar. Surrounding the pillar are gate insulating and conductor layers connected to a plate line (PL) and a word line (WL). Voltage control on the SL, PL, WL, and BL enables data retention by holding holes in the Si pillar’s channel region and data erasure by removing the holes.

Patent №: 12100443 (September 24, 2024) – Semiconductor-element-including memory device. A memory device writes and erases data by controlling voltages on gate and impurity layers. Cells are connected to source, bit, word, and control lines. During reading, data is sent to bit lines, while non-selected pages receive zero or negative voltage.

He has also served as an Adjunct Professor in Chemical Engineering at the University of California, contributing to both academia and industry. His collaboration with Professor Mark Davis from Caltech on the fundamentals of zeolite synthesis has been particularly influential. Dr. Zones’ achievements include receiving the 2001 Breck Award from the International Zeolite Association and the 2007 Houdry Award from the North American Catalysis Society for his contributions to applied catalysis.

Additionally, in recognition of his impact on the field, Dr. Zones was elected to the United States National Academy of Engineering, one of the highest honors for engineers in the U.S.

Patent №: 12097485 (September 24, 2024) – Small crystal SSZ-41, its synthesis and use. A method for producing small crystal, high-aluminum zincoaluminosilicate materials with the SSZ-41 structure is disclosed, along with the resulting compositions and their applications.

Patent №: D1043680 (September 24, 2024) – Head-mounted display.

Patent №: D1043679 (September 24, 2024) – Head-mounted display.

Patent №: D1043678 (September 24, 2024) – Head-mounted display.

Patent №: D1043677 (September 24, 2024) – Head-mounted display.

Patent №: D1043674 (September 24, 2024) – Head-mounted display.