Memory device using semiconductor elements

Abstract

Provided on a substrate are an Nlayer connecting to a source line SL and an Nlayer connecting to a bit line BL that are located at opposite ends of a Si pillar standing in an upright position along the vertical direction, an N layer continuous with the Nlayer, an N layer continuous with the Nlayer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connecting to a plate line PL, and a second gate conductor layer surrounding a second gate insulating layer surrounding the Si pillar and connecting to a word line WL. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data retention operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region of the Si pillar, and a data erase operation for removing the holes from the channel region.