The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Apr. 29, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, KR;

Inventors:

Sung-Il Chang, Hwaseseong-si, KR;

Changhyun Lee, Suwon-si, KR;

Byoungkeun Son, Suwon-si, KR;

Jin-Soo Lim, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 29/4232 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/31111 (2013.01); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H01L 29/42372 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.


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