The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2020

Filed:

Oct. 28, 2014
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Kouta Tomita, Ibo Hyogo, JP;

Noboru Matsuda, Ibo Hyogo, JP;

Hideyuki Ura, Tatsuno Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2005.12); H01L 31/062 (2011.12); H01L 29/78 (2005.12); H01L 29/06 (2005.12); H01L 29/417 (2005.12); H01L 29/40 (2005.12); H01L 29/423 (2005.12);
U.S. Cl.
CPC ...
H01L 29/7813 (2012.12); H01L 29/0653 (2012.12); H01L 29/0696 (2012.12); H01L 29/41741 (2012.12); H01L 29/41766 (2012.12); H01L 29/7811 (2012.12); H01L 29/0657 (2012.12); H01L 29/0661 (2012.12); H01L 29/402 (2012.12); H01L 29/404 (2012.12); H01L 29/407 (2012.12); H01L 29/42372 (2012.12);
Abstract

In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.


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