The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2017

Filed:

Mar. 30, 2014
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Deepak Chandra Sekar, Mountain View, CA (US);

Nima Mokhlesi, Los Gatos, CA (US);

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2005.12); G11C 5/14 (2005.12); G11C 16/10 (2005.12); G11C 16/26 (2005.12); G11C 29/04 (2005.12);
U.S. Cl.
CPC ...
G11C 5/146 (2012.12); G11C 16/10 (2012.12); G11C 16/26 (2012.12); G11C 2029/0409 (2012.12);
Abstract

Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.


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