The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2016

Filed:

May. 20, 2014
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Chun-Hung Lai, Kamakura, JP;

Deepanshu Dutta, San Jose, CA (US);

Shinji Sato, Chigasaki, JP;

Gerrit Jan Hemink, Yokohama, JP;

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2005.12); G11C 11/56 (2005.12); G11C 16/10 (2005.12); G11C 16/04 (2005.12);
U.S. Cl.
CPC ...
G11C 11/5628 (2012.12); G11C 16/0483 (2012.12); G11C 16/10 (2012.12);
Abstract

Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.


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