Integrated circuit device having stacked dies and impedance balanced transmission lines

Abstract

A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack. In yet another embodiment, two or more stacks of integrated circuit die are disposed in the multi-chip device and the one or more multi-drop transmission lines may be implemented in the flow-through approach. The plurality of integrated circuit die may comprise a plurality of memory devices, or a plurality of memory devices and a controller, or a plurality of controllers and a plurality of memory devices.