The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2011
Filed:
Mar. 06, 2002
Vishram Prakash Dalvi, Folsom, CA (US);
Rodney R. Rozman, Placerville, CA (US);
Christopher John Haid, Folsom, CA (US);
Jerry Kreifels, El Dorado Hills, CA (US);
Joseph Tsang, Elk Grove, CA (US);
Jeff Evertt, Kirkland, WA (US);
Jahanshir J. Javanifard, Sacramento, CA (US);
Jeffrey J. Peterson, Folsom, CA (US);
Vishram Prakash Dalvi, Folsom, CA (US);
Rodney R. Rozman, Placerville, CA (US);
Christopher John Haid, Folsom, CA (US);
Jerry Kreifels, El Dorado Hills, CA (US);
Joseph Tsang, Elk Grove, CA (US);
Jeff Evertt, Kirkland, WA (US);
Jahanshir J. Javanifard, Sacramento, CA (US);
Jeffrey J. Peterson, Folsom, CA (US);
Abstract
A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.