The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jan. 06, 2017
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Jared L. Zerbe, Woodside, CA (US);

Bruno W. Garlepp, Sunnyvale, CA (US);

Pak S. Chau, Saratoga, CA (US);

Kevin S. Donnelly, Los Altos, CA (US);

Mark A. Horowitz, Menlo Park, CA (US);

Stefanos Sidiropoulos, Palo Alto, CA (US);

Billy W. Garrett, Jr., Charleston, SC (US);

Carl W. Werner, Los Gatos, CA (US);

Assignee:

RAMBUS INC., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/00 (2015.01); H04L 25/03 (2006.01); H04L 25/49 (2006.01); H04L 25/02 (2006.01); H04L 7/033 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
H04L 25/4917 (2013.01); G06F 13/1678 (2013.01); G06F 13/4068 (2013.01); G11C 7/1051 (2013.01); G11C 8/10 (2013.01); H04L 7/0331 (2013.01); H04L 25/0272 (2013.01); H04L 25/0296 (2013.01); H04L 25/03006 (2013.01);
Abstract

An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.


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