The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Nov. 19, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ganesh Balamurugan, Hillsboro, OR (US);

Mozhgan Mansuri, Portland, OR (US);

Sami Hyvonen, Beaverton, OR (US);

Bryan K. Casper, Portland, OR (US);

Frank O'Mahony, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); G11C 7/22 (2006.01); H03K 5/156 (2006.01); H04L 25/03 (2006.01); H04B 1/04 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); H03K 5/1565 (2013.01); H04B 1/04 (2013.01); H04L 25/03 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01);
Abstract

Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.


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