The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
Jan. 24, 2017
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ming-Chieh Huang, San Jose, CA (US);
Chan-Hong Chern, Palo Alto, CA (US);
Tsung-Ching (Jim) Huang, Mountain View, CA (US);
Chih-Chang Lin, San Jose, CA (US);
Tien-Chun Yang, San Jose, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A delay line circuit includes: a coarse-tuning arrangement, including delay units; and a fine-tuning arrangement including at least three serially-connected inverters. The coarse-tuning arrangement is configured to receive an input signal and coarsely-tune the input signal, the coarsely-tuning including transferring the input signal through a selected number of the delay units and thereby producing a first output signal. The fine-tuning arrangement is configured to receive the first output signal, finely-tune the first output signal, and produce a second output signal, the finely-tuning including selectively connecting a speed control unit to a node between a corresponding pair of the at least three serially-connected inverters.