The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jul. 24, 2017
Applicant:

Te Connectivity Corporation, Berwyn, PA (US);

Inventors:

Graham Harry Smith, Jr., Mechanicsburg, PA (US);

Scott Eric Walton, Mount Joy, PA (US);

Albert Tsang, Harrisburg, PA (US);

Assignee:

TE CONNECTIVITY CORPORATION, Berwyn, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 12/00 (2006.01); H01R 13/6461 (2011.01); H01R 12/72 (2011.01); H01R 12/73 (2011.01); H01R 12/70 (2011.01);
U.S. Cl.
CPC ...
H01R 13/6461 (2013.01); H01R 12/7005 (2013.01); H01R 12/721 (2013.01); H01R 12/732 (2013.01);
Abstract

A shroud that forms part of an electrical connector for securing a plurality of circuit wafers within the electrical connector includes a top wall, a bottom wall, and a plurality of vertical members extending between the top and bottom walls that define a plurality of slots for receiving the plurality of circuit wafers. Each vertical member includes a first side that faces a second side of an adjacent vertical member. The first side defines top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a first distance, and first and second recessed surface regions between the top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a second distance that is greater than the first distance. The first and second recessed surface regions are positioned so as to prevent direct contact between the vertical members and one or more high-frequency traces disposed on the plurality of circuit wafers.


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