The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Nov. 19, 2014
Applicant:

William Marsh Rice University, Houston, TX (US);

Inventors:

James M. Tour, Bellaire, TX (US);

Gunuk Wang, Houston, TX (US);

Yang Yang, Beijing, CN;

Yongsung Ji, Houston, TX (US);

Assignee:

William Marsh Rice University, Houston, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/16 (2006.01); H01L 29/41 (2006.01); H01L 27/24 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1675 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01); H01L 29/1606 (2013.01); H01L 29/413 (2013.01); H01L 45/04 (2013.01); H01L 45/1253 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); H01L 45/1608 (2013.01); H01L 45/1641 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01);
Abstract

A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiO) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.


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