Resistive memory with varying dopant concentration in select transistor channel

Abstract

A nonvolatile semiconductor memory device according to one embodiment includes: a first wiring extending in a first direction as a longitudinal direction thereof; a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction; a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; a select transistor having one end connected to the second wiring; and a third wiring connected to the other end of the select transistor. A semiconductor layer included in the select transistor has a first impurity concentration at the second end. An impurity concentration of the semiconductor layer decrease to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end.