The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Sep. 28, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Timothy A. Brunner, Ridgefield, CT (US);

Oleg Gluschenkov, Tannersville, NY (US);

Donghun Kang, Hopewell Junction, NY (US);

Byeong Y. Kim, Lagrangeville, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/266 (2006.01); H01L 21/306 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02016 (2013.01); H01L 21/266 (2013.01); H01L 21/30604 (2013.01); H01L 21/30625 (2013.01); H01L 22/12 (2013.01);
Abstract

A method of forming a semiconductor wafer includes generating a stress topography model of a semiconductor wafer with a plurality of desired structures in a desired layout. The method also includes determining a topography and calculating a compensation pattern based upon the topography, wherein the compensation pattern balances wafer topography. The method also includes patterning a semiconductor front side with the plurality of desired microstructures in the desired layout. The method also includes patterning the semiconductor back side with a compensation block mask corresponding to the compensation pattern.


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