The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
Apr. 13, 2017
Cypress Semiconductor Corporation, San Jose, CA (US);
Joseph S Tandingan, Colorado Springs, CO (US);
David W. Still, Colorado Springs, CO (US);
Jesse J Siman, San Jose, CA (US);
Jayant Ashokkumar, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.