The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jan. 10, 2017
Applicant:

National University of Singapore, Singapore, SG;

Inventors:

Xuepeng Qiu, Singapore, SG;

William Sylvain Legrand, Singapore, SG;

Hyunsoo Yang, Singapore, SG;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/161 (2013.01); G11C 11/1675 (2013.01); H01L 27/228 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01);
Abstract

In one embodiment, a SO-STT device has a non-symmetric device geometry. The device may be fabricated to have a non-symmetric magnetic pattern by tilting a shaped magnetic pattern (e.g., an ellipse, diamond, rectangle, etc. shaped magnetic pattern) such that the pattern's main (long and short) axes are tilted with respected to an in-plane current direction. Alternatively, the non-symmetric device geometry may be produced by locating the magnetic pattern away from the center of a current injection line. The non-symmetric may permit switching absent application of an external magnetic field. A SO-STT device with non-symmetric device geometry, or another type of SO-STT device, may further integrate an additional semiconductor, insulator or metal layer into the device's multilayer stack. By integrating the additional semiconductor, insulator or metal layer, a significant reduction of SO-STT switching current density may be achieved. Depending on the embodiment, the additional semiconductor, insulator or metal layer may be disposed adjacent to the FM layer, or within the FM layer, among other possibilities.


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