The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
Mar. 31, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Lakshminarayana Pappu, Folsom, CA (US);
Baruch Schnarch, Zichron-Ya'akov, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G01R 31/28 (2006.01); H01L 25/065 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2853 (2013.01); H01L 25/0657 (2013.01); H03K 19/1776 (2013.01); H03K 19/17736 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06555 (2013.01);
Abstract
Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.