The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Nov. 28, 2016
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Masanori Tsutsumi, Yokkaichi, JP;

Kengo Kajiwara, Yokkaichi, JP;

Raghuveer S. Makala, Campbell, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11582 (2017.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 27/11573 (2017.01); H01L 27/11568 (2017.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02236 (2013.01); H01L 21/28282 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/0847 (2013.01); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/6656 (2013.01);
Abstract

A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.


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