The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Jun. 13, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Zhibiao Zhou, Singapore, SG;

Ding-Lung Chen, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/423 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 49/02 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 23/528 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1255 (2013.01); H01L 28/60 (2013.01); H01L 29/42356 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01);
Abstract

A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged in an array and electrically connected to corresponding bit lines and word lines respectively, and any two memory cells adjacent to each other share a same oxide semiconductor layer as a channel layer. The present invention also relates to a semiconductor memory device including two memory cells sharing a same oxide semiconductor layer as a channel layer.


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